#ifndef __UOTG_GENERAL_REGS_H_
#define __UOTG_GENERAL_REGS_H_

#ifdef __cplusplus
extern "C"{
#endif

#include "typedef.h"


#define UOTG_DISABLE	0
#define UOTG_ENABLE		1

//General Control Register
//Name: UOTGHS_CTRL
//Address: 0x400AC800
//Access: Read-write
typedef union _UotgCtrlReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
#ifdef BIG_ENDIAN
		uint32 reserved26_31 	: 6; // bit 26-31 
		uint32 uOtgMode 		: 1; // bit 25, UIMOD: UOTGHS Mode, 0=Host, 1=Device
		uint32 uOtgIdPinEn		: 1; // bit 24, UIDE: UOTGID Pin Enable, The USB mode (device/host) is selected.., 0=from the UIMOD bit, 1=from the UOTGID input pin.
		uint32 reserved23 		: 1; // bit 23
		uint32 timerAccUnlock	: 1; // bit 22, TUNLOCK: Timer Access Unlock, 0: The TIMPAGE and TIMVALUE fields are locked, 1: The TIMPAGE and TIMVALUE fields are unlocked
		uint32 timePage 		: 2; // bit 20-21, TIMPAGE: Timer Page
		uint32 reserved18_19 	: 2; // bit 18-19
		uint32 timeValue 		: 2; // bit 16-17, TIMVALUE: Timer Value
		uint32 uOtgEn			: 1; // bit 15, USBE: UOTGHS Enable, 0: The UOTGHS is disabled
									 
		uint32 freezeClk 		: 1; // bit 14, Freeze USB Clock
		uint32 vBusPolarityOff	: 1; // bit 13, VBus Polarity Off
		uint32 otgPageEn 		: 1; // bit 11, OTG Pad Enable
		uint32 hnpreq 			: 1; // bit 12, HNP Request
		uint32 srpreq 			: 1; // bit 10, SRP Request
		uint32 srpsel 			: 1; // bit 9, SRP Selection
		uint32 vbushwc 			: 1; // bit 8, VBus Hardware Control
		uint32 susTimeOutEn		: 1; // bit 7, Suspend Time-Out Interrupt Enable
		uint32 hnpErrIntEn 		: 1; // bit 6, HNP Error Interrupt Enable
		uint32 roleExchIntEn	: 1; // bit 5, ROLEEXE: Role Exchange Interrupt Enable
		uint32 BCntErrIntEn 	: 1; // bit 4, BCERRE: B-Connection Error Interrupt Enable
		uint32 vBusErrIntEn		: 1; // bit 3, VBERRE: VBus Error Interrupt Enable
		uint32 srpIntEn 		: 1; // bit 2, SRPE: SRP Interrupt Enable
		uint32 vBusTranIntEn	: 1; // bit 1, VBUSTE: VBus Transition Interrupt Enable
		uint32 IdTranIntEn		: 1; // bit 0, IDTE: ID Transition Interrupt Enable
#else
		uint32 IdTranIntEn		: 1; // bit 0, IDTE: ID Transition Interrupt Enable
		uint32 vBusTranIntEn	: 1; // bit 1, VBUSTE: VBus Transition Interrupt Enable
		uint32 srpIntEn 		: 1; // bit 2, SRPE: SRP Interrupt Enable
		uint32 vBusErrIntEn		: 1; // bit 3, VBERRE: VBus Error Interrupt Enable
		uint32 BCntErrIntEn 	: 1; // bit 4, BCERRE: B-Connection Error Interrupt Enable
		uint32 roleExchIntEn	: 1; // bit 5, ROLEEXE: Role Exchange Interrupt Enable
		uint32 hnpErrIntEn 		: 1; // bit 6, HNP Error Interrupt Enable
		uint32 susTimeOutEn		: 1; // bit 7, Suspend Time-Out Interrupt Enable
		uint32 vbushwc 			: 1; // bit 8, VBus Hardware Control
		uint32 srpsel 			: 1; // bit 9, SRP Selection
		uint32 srpreq 			: 1; // bit 10, SRP Request
		uint32 hnpreq 			: 1; // bit 12, HNP Request
		uint32 otgPageEn 		: 1; // bit 11, OTG Pad Enable
		uint32 vBusPolarityOff	: 1; // bit 13, VBus Polarity Off
		uint32 freezeClk 		: 1; // bit 14, Freeze USB Clock
		uint32 uOtgEn			: 1; // bit 15, USBE: UOTGHS Enable, 0: The UOTGHS is disabled
		uint32 timeValue 		: 2; // bit 16-17, TIMVALUE: Timer Value
		uint32 reserved18_19 	: 2; // bit 18-19
		uint32 timePage 		: 2; // bit 20-21, TIMPAGE: Timer Page
		uint32 timerAccUnlock	: 1; // bit 22, TUNLOCK: Timer Access Unlock, 0: The TIMPAGE and TIMVALUE fields are locked, 1: The TIMPAGE and TIMVALUE fields are unlocked
		uint32 reserved23 		: 1; // bit 23
		uint32 uOtgIdPinEn		: 1; // bit 24, UIDE: UOTGID Pin Enable, The USB mode (device/host) is selected.., 0=from the UIMOD bit, 1=from the UOTGID input pin.
		uint32 uOtgMode 		: 1; // bit 25, UIMOD: UOTGHS Mode, 0=Host, 1=Device
		uint32 reserved26_31 	: 6; // bit 26-31 
#endif
	};
}UotgCtrlReg;

//General Status Register
//Name: UOTGHS_SR
//Address: 0x400AC804
//Access: Read-only
typedef union _UotgStatusClsReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 IdTranIntCls		: 1; // bit 0, IDTI: ID Transition Interrupt
		uint32 vBusTranIntCls	: 1; // bit 1, VBUSTI: VBus Transition Interrupt
		uint32 srpIntCls	 	: 1; // bit 2, SRPI: SRP Interrupt
		uint32 vBusErrIntCls	: 1; // bit 3, VBERRI: VBus Error Interrupt
		uint32 BCntErrIntCls	: 1; // bit 4, BCERRI: B-Connection Error Interrupt
		uint32 roleExchIntCls	: 1; // bit 5, ROLEEXI: Role Exchange Interrupt
		uint32 hnpErrIntCls 	: 1; // bit 6, HNPERRIC: HNP Error Interrupt Clear
		uint32 susTimeOutIntCls	: 1; // bit 7, STOIC: Suspend Time-Out Interrupt Clear
		
		uint32 reserved8 		: 1; // bit 8, 
		uint32 vBusReqCls		: 1; // bit 9, VBUSRQC: VBus Request Clear
		uint32 reserved10_31 	: 22; // bit 10-31 
	};
}UotgStatusClsReg;


//General Status Set Register
//Name: UOTGHS_SFR
//Address: 0x400AC80C
//Access: Write-only
typedef union _UotgStatusSetReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 IdTranIntSet		: 1; // bit 0, IDTIS: ID Transition Interrupt Set
		uint32 vBusTranIntSet	: 1; // bit 1, VBUSTIS: VBus Transition Interrupt Set
		uint32 srpIntSet	 	: 1; // bit 2, SRPIS: SRP Interrupt Set
		uint32 vBusErrIntSet	: 1; // bit 3, VBERRIS: VBus Error Interrupt Set
		uint32 BCntErrIntSet	: 1; // bit 4, BCERRIS: B-Connection Error Interrupt Set
		uint32 roleExchIntSet	: 1; // bit 5, ROLEEXIS: Role Exchange Interrupt Set
		uint32 hnpErrIntSet 	: 1; // bit 6, HNPERRIS: HNP Error Interrupt Set
		uint32 susTimeOutIntSet	: 1; // bit 7, STOIS: Suspend Time-Out Interrupt Set
		
		uint32 reserved8 		: 1; // bit 8, 
		uint32 vBusReqSet		: 1; // bit 9, VBUSRQS: VBus Request Set
		uint32 reserved10_31 	: 22; // bit 10-31 
	};
}UotgStatusSetReg;

typedef enum _OtgState
{
	  A_IDLESTATE = 0
	, A_WAIT_VRISE
	, A_WAIT_BCON
	, A_HOST
	, A_SUSPEND
	, A_PERIPHERAL = 5
	, A_WAIT_VFALL
	, A_VBUS_ERR
	, A_WAIT_DISCHARGE
	, B_IDLE
	, B_PERIPHERAL	= 10
	, B_WAIT_BEGIN_HNP
	, B_WAIT_DISCHARGE
	, B_WAIT_ACON
	, B_HOST
	, B_SRP_INIT = 15
}OtgState;

//General Finite State Machine Register
//Name: UOTGHS_FSM
//Address: 0x400AC82C
//Access: Read-only
typedef union _UotgFsmReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 otgState		: 4; // bit 0-4, DRDSTATE, This field indicates the state of the UOTGHS, Ref the defintion of OtgState
		uint32 reserved4_31 : 28; // bit 4-31 
	};
}UotgFsmReg;

#ifdef __cplusplus
}
#endif

#endif

